// ****************************************************************************** 
// Copyright     :  Copyright (C) 2018, Hisilicon Technologies Co. Ltd.
// File name     :  usb3_dev_reg_offset.h
// Project line  :  Platform And Key Technologies Development
// Department    :  CAD Development Department
// Author        :  xxx
// Version       :  1
// Date          :  2013/3/10
// Description   :  The description of xxx project
// Others        :  Generated automatically by nManager V4.2 
// History       :  xxx 2018/04/10 11:53:38 Create file
// ******************************************************************************

#ifndef __USB3_DEV_REG_OFFSET_H__
#define __USB3_DEV_REG_OFFSET_H__

/* USB3_DEV Base address of Module's Register */
#define SOC_USB3_DEV_BASE                       (0xc700)

/******************************************************************************/
/*                      SOC USB3_DEV Registers' Definitions                            */
/******************************************************************************/

#define SOC_USB3_DEV_DCFG_REG            (SOC_USB3_DEV_BASE + 0xC700) /* Device Configuration Register */
#define SOC_USB3_DEV_DCTL_REG            (SOC_USB3_DEV_BASE + 0xC704) /* Device Control Register */
#define SOC_USB3_DEV_DEVTEN_REG          (SOC_USB3_DEV_BASE + 0xC708) /* Device Event Enable Register */
#define SOC_USB3_DEV_DSTS_REG            (SOC_USB3_DEV_BASE + 0xC70C) /* Device Status Register */
#define SOC_USB3_DEV_DGCMDPAR_REG        (SOC_USB3_DEV_BASE + 0xC710) /* Device Generic Command Parameter Register */
#define SOC_USB3_DEV_DGCMD_REG           (SOC_USB3_DEV_BASE + 0xC714) /* Device Generic Command Register */
#define SOC_USB3_DEV_DALEPENA_REG        (SOC_USB3_DEV_BASE + 0xC720) /* Device Active USB Endpoint Enable Register */
#define SOC_USB3_DEV_RSVD_REG            (SOC_USB3_DEV_BASE + 0xC7A0) /* Reserved */
#define SOC_USB3_DEV_DEPCMDPAR2[0:7]_REG (SOC_USB3_DEV_BASE + 0xC9F0) /* Device Physical Endpoint-n Command Parameter 2 Register */
#define SOC_USB3_DEV_DEPCMDPAR1[0:7]_REG (SOC_USB3_DEV_BASE + 0xC9F4) /* Device Physical Endpoint-n Command Parameter 1 Register */
#define SOC_USB3_DEV_DEPCMDPAR0[0:7]_REG (SOC_USB3_DEV_BASE + 0xC9F8) /* Device Physical Endpoint-n Command Parameter 0 Register */
#define SOC_USB3_DEV_DEPCMD[0:7]_REG     (SOC_USB3_DEV_BASE + 0xC9FC) /* Device Physical Endpoint-n Command Register */
#define SOC_USB3_DEV_DEV_IMOD[0]_REG     (SOC_USB3_DEV_BASE + 0xC8A0) /* Device Interrupt Moderation Register (DEV_IMOD) */

#endif // __USB3_DEV_REG_OFFSET_H__
